[PATCH v8 RESEND 1/5] Docs/LoongArch: Add Advanced Extended-Redirect IRQ model description
#UpdatedFrom:Tianyang Zhang <zhangtianyang@loongson.cn>
Date:
Message-ID:<20251217012322.41701-2-zhangtianyang@loongson.cn>
Patch:v8 · 1/5
Language:zh_CN
Patch-ID:6a3e26443652efa74b069d33d5bf46baaf9c8214
Files:
Documentation/arch/loongarch/irq-chip-model.rstDocumentation/translations/zh_CN/arch/loongarch/irq-chip-model.rstLinks:lore message ↗ · raw mail ↗
Patch content 2 changed files
Introduce the redirect interrupt controllers.When the redirect interruptcontroller is enabled, the routing target of MSI interrupts is no longera specific CPU and vector number, but a specific redirect entry. Theactual CPU and vector number used are described by the redirect entry. Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>--- .../arch/loongarch/irq-chip-model.rst | 38 +++++++++++++++++++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 ++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rstindex a7ecce11e445..d9a2e8d7f70e 100644--- a/Documentation/arch/loongarch/irq-chip-model.rst+++ b/Documentation/arch/loongarch/irq-chip-model.rst@@ -181,6 +181,44 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: | Devices | +---------+ +Advanced Extended IRQ model (with redirection)+==============================================++In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go+to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go+to REDIRECT for remapping it to AVEC, and then go to CPUINTC directly, while all+other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then+go to CPUINTC directly::++ +-----+ +-----------------------+ +-------++ | IPI | --> | CPUINTC | <-- | Timer |+ +-----+ +-----------------------+ +-------++ ^ ^ ^+ | | |+ +---------+ +----------+ +---------+ +-------++ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |+ +---------+ +----------+ +---------+ +-------++ ^ ^+ | |+ | +----------++ | | REDIRECT |+ | +----------++ | ^+ | |+ +---------+ +---------++ | PCH-PIC | | PCH-MSI |+ +---------+ +---------++ ^ ^ ^+ | | |+ +---------+ +---------+ +---------++ | Devices | | PCH-LPC | | Devices |+ +---------+ +---------+ +---------++ ^+ |+ +---------++ | Devices |+ +---------++ ACPI-related definitions ======================== diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rstindex d4ff80de47b6..7e4e3e55c7ad 100644--- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst+++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst@@ -174,6 +174,43 @@ CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断发送到AVECINTC, | Devices | +---------+ +高级扩展IRQ模型 (带重定向)+==========================++在这种模型里面,IPI(Inter-Processor Interrupt)和CPU本地时钟中断直接发送到CPUINTC,+CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断首先发送到REDIRECT模块,完成重定向后发+送到AVECINTC,而后通过AVECINTC直接送达CPUINTC,而其他所有设备的中断则分别发送到所连+接的PCH-PIC/PCH-LPC,然后由EIOINTC统一收集,再直接到达CPUINTC::++ +-----+ +-----------------------+ +-------++ | IPI | --> | CPUINTC | <-- | Timer |+ +-----+ +-----------------------+ +-------++ ^ ^ ^+ | | |+ +---------+ +----------+ +---------+ +-------++ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |+ +---------+ +----------+ +---------+ +-------++ ^ ^+ | |+ | +----------++ | | REDIRECT |+ | +----------++ | ^+ | |+ +---------+ +---------++ | PCH-PIC | | PCH-MSI |+ +---------+ +---------++ ^ ^ ^+ | | |+ +---------+ +---------+ +---------++ | Devices | | PCH-LPC | | Devices |+ +---------+ +---------+ +---------++ ^+ |+ +---------++ | Devices |+ +---------++ ACPI相关的定义 ============== -- 2.41.0